1. Field of the Invention
The present invention relates generally to a semiconductor structure and a process thereof, and more specifically to a semiconductor structure having four gate channels and a process thereof.
2. Description of the Prior Art
With the increasing miniaturization of semiconductor devices, various Multi-gate MOSFET devices have been developed. The Multi-gate MOSFET is advantageous for the following reasons. First, the manufacturing processes of the Multi-gate MOSFET devices can be integrated into traditional logic device processes, and thus are more compatible. In addition, since the three-dimensional structure of the Multi-gate MOSFET increases the overlapping area between the gate and the substrate, the channel region is controlled more effectively. This therefore reduces the drain-induced barrier lowering (DIBL) effect and the short channel effect. Moreover, the channel region is longer for a similar gate length. Therefore, the current between the source and the drain is increased.
Multi-gate MOSFETs all have fin-shaped structures, and gates are disposed on the fin-shaped structures to form the three dimensional MOSFETs (which are different from the planar MOSFETs). The height of the fin-shaped structures and the width of the gates disposed on the fin-shaped structures will affect the width and the length of the gate channels of the multi-gate MOSFETs. In the layouts of integrated circuits, the purposes of each multi-gate MOSFETs are different and the electrical requirements for these MOSFETS are therefore different as well, thereby leading these corresponding fin-shaped structures to have different heights. However, the different heights of the fin-shaped structures increase the processing difficulties, and therefore increase the number of problems during the processes, such as over-polishing or insufficient polishing of the gates disposed across each of the fin-shaped structures.